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Bridging biological neural architectures with silicon — from transistor-level SRAM to spiking neural networks on FPGA.
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I'm a third-year Electronics & Computer Science student at Vidyalankar Institute of Technology, Mumbai, with a deep passion for understanding computing at its most fundamental level — the transistor.
My journey started with building circuits from raw logic gates, deliberately avoiding microcontrollers to truly understand digital design. That instinct to reach for the transistor before the library call now drives my research in neuromorphic computing and VLSI design.
I believe the next generation of computing will look less like a CPU and more like a brain. My work sits at that intersection — designing hardware that processes information the way biological systems do: efficiently, adaptively, and at ultra-low power.
B.Tech, ECE
VIT Mumbai | 9.44 CGPA
Gold Medal in CS (10th)
Neuromorphic Computing
SRAM Design & Analysis
Spiking Neural Networks
NPTEL Silver Medal
Hackathon Winner
District Badminton Champ
Vidyalankar Institute of Technology · 180nm CMOS · Cadence Virtuoso
Performed butterfly curve analysis and DC sweep characterization comparing 6T and 12T SRAM topologies. Demonstrated that 12T cells eliminate read disturb entirely and enable sub-0.5V operation with 9× dynamic power reduction — at the cost of 4.82× area overhead. Directly relevant to ultra-low-power IoT, biomedical SoCs, and neuromorphic memory arrays.
Exploring the design space of hardware-efficient brain-inspired computing. Currently studying Artificial Neural Networks (ANN) and Spiking Neural Networks (SNN) with a focus on translating biological neuron dynamics — synaptic plasticity, membrane potentials, spike-timing-dependent plasticity (STDP) — into scalable CMOS and FPGA implementations.
Designed a complete 32-bit RISC-V processor with 16-bit ALU, external memory interfacing, and multi-sensor peripheral integration (DHT11, ultrasonic, IR) on Xilinx FPGA.
Hardware spike generator emulating biological neuron spiking behavior using stochastic RNG-based neuron models. Targeting minimal power and resource utilization for edge neuromorphic applications.
Reusable IP core for UART-to-BLE data bridging. Deployed in a smart-home prototype enabling real-time mobile-to-FPGA control of lights and motors via Bluetooth.
IIT Bombay's E-Yantra robotics competition. Designed a maze-solving algorithm implemented entirely in Verilog with FSM-controlled multi-sensor integration.
Touch-sensitive musical instrument on FPGA using frequency modulation and scaling techniques for accurate multi-octave tone synthesis.
Multi-process Electron + Python desktop app integrating Mistral AI & Gemini Vision API. Features multi-process IPC, thread-safe keystroke monitoring, voice-to-text, and <200ms latency. 42 unit tests.
Full-stack real-time inventory management system with SQL backend, dual-login portal, low-stock alerts, and profit tracking. Deployed in multiple retail stores.
Fastest Finger First game, Ultrasonic Radar (30m range), Peltier liquid cooler with live temp readout — all built with discrete gates and flip-flops, zero microcontrollers.
Prosmart Solutions, India
Vidyalankar Institute of Technology, Mumbai
Joy of Computing using Python — IIT Madras (81%)
DigiGo Hardware Hackathon
Zero-True International Hackathon
Badminton · 4th in Intra-State
Under-13 National Level Representative
Computer Science — 10th Standard (ICSE)
Open to research collaborations, internship opportunities, and conversations about neuromorphic computing and VLSI design.